1. Field of the Invention
The present invention relates to a symbol timing recovery circuit that recovers the symbol timing of an input signal.
2. Description of the Related Art
In general, recovery of a received signal in a communication system requires recovery of the symbol timing from the received signal. In the following description, a symbol timing recovery circuit described in Patent Document 1 (Japanese Patent No. 3573627) is explained with reference to FIG. 1.
In FIG. 1, an analog-to-digital (A/D) converter 1 converts an input signal (or a received signal) into a digital signal. The sampling rate of the A/D converter 1, fsamp, is the same or more than twice as fast as the symbol rate of an input signal, fs (That is to say, “fsamp≧fs). A FIR (Finite Impulse Response) filter 2 functions as an interpolator and obtains data at a data decision point and data at a zero-crossing point from a digital data string obtained by the A/D converter 1. A decimation circuit 3, when data obtained from the FIR filter 2 overlap, decimates one of the overlapped data.
A phase comparator 4 calculates an error between the data output from the decimation circuit 3 and the data at an ideal sampling point. A loop filter 5 smoothes (or averages) the outputs of the phase comparator 4. Numerically Controlled Oscillator (NCO) 6 operates as an integrator of infinite phase and oscillates at a frequency according to the output of the loop filter 5. A tap coefficient computing unit 7 calculates tap coefficients (a0-a4) to be provided to the FIR 2 based on the output signal of the NCO 6. A clock control circuit 8 generates a decimated (or partially inhibited) clock CLK2 from a sampling clock CLK1 based on the output signal of the NCO 6.
In the symbol timing recovery circuit of the above configuration, at the timing of the decimation clock CLK2, a value (data) at the data decision point and a value (data) at the zero-crossing point are alternately output. In other words, symbol timing is recovered.
It should be noted that Patent Document 2 (Japanese Patent Application Publication No. 2006-279332) describes a timing recovery circuit comprising a first oscillating circuit for outputting a first timing signal to an output terminal, a second oscillating circuit for outputting a second timing signal to an output terminal, a first decimation circuit coupled to a supply terminal of the first clock signal and to the output terminal of the first oscillating circuit and outputs the second clock signal to the output terminal by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the output terminal of the first decimation circuit and to the output terminal of the second oscillating circuit and outputs a third clock signal to the output terminal by decimating pulses of the second clock signal in response to the second timing signal. Either one of the first timing signal or the second timing signal has a fixed cycle, and the other one has a cycle responsive to feedback control.
FIG. 2 is a diagram showing spectrum of the output signal of the symbol timing recovery circuit shown in FIG. 1. Note that the spectrum is obtained by a simulation of a 6M baud 256-QAM modulated signal.
As shown in FIG. 2, in the conventional symbol timing recovery circuit, a sideband wave that is not present in the input signal is generated. The sideband wave contains a frequency component corresponding to the frequency of the clock decimation, and its harmonic wave. The sideband wave causes deterioration of recovery accuracy of the symbol timing. The deterioration of recovery accuracy of the symbol timing would cause deterioration of BER (Bit Error Rate) characteristics.